Artec Design develops and maintains an FPGA based modem core with supporting modules, that enables the creation of up to 1 Gb/s P2P wireless links. The core was designed for cheap FPGAs, therefore, low FPGA resource consumption was targeted during the development, e.g. the DSPs are used serially at higher clock rates to complete several multiplications per single DSP symbol clock cycle.
A typical usage scenario of the modem core is shown in the figure below, with the modem core, Ethernet, configuration and converter interfaces placed in the FPGA. A GUI utility allows to configure modem modes and the debug link with spectral and constellation plots. The example design is configured via serial or SPI interface. Several radio circuits are supported e.g. AD9361, IE1000 operating in 5 GHz region. Ethernet from FPGA connects to on-board PHY and Gbit copper cable. A single channel modem together with the example design fits into Xilinx Artix-50 FPGAs with slowest speed grade 1. Dual channel XPIC requires doubled resources for Artix-100 with slowest speed grade 1.
The modem core shown in the figure below is dual channel and supports both TDD and FDD modes. Data is split between horizontal and vertical channels during transmission and is merged in the receiver. All interfaces follow AXI streaming standard. The single channel modem omits the split and merge phase. Both single and dual channel DSP blocks work up to 72 MHz / 8-bit QAM256 for 576 Mb/s uncoded data. For 226 / 252 coding rate Ethernet coded speed is 516 Mb/s per single channel or over Gb/s for dual channel. Artec Design has also developed an LDPC core that can be used instead of Xilinx RS core. LDPC provides 6 dB better SNR but requires twice the resources when compared to RS.
The modem core can be included in various products where the modem is placed in the same FPGA as the application-specific blocks. Current use-cases include visible light and free-space optical communications, with 300+ Mb/s at 100+ meters, as well as backhaul solutions. However, potential applications are not limited to existing solutions.
- Multiple modem core designs:
- 5-80MHz dual core for Artix 100
- 50-500MHz single core for Kintex 325
- C API for modem control, GUI for debug and configuration
- Full-duplex (FDD) as well as half-duplex (TDD) with QPSK-QAM256
- Built-in hardware ACM engine based on BER and modulation error vector MSE
- XPI cancelling (assumes synchronized TX local oscillators)
- Xilinx hard-decision Reed-Solomon or custom soft-decision LDPC FEC
- Fully digital symbol clock recovery and carrier frequency error compensation
- TX and RX group delay equalization
- I&O frequency dependent imbalance compensation
- Recovery of low frequency components in the demodulator
- Integrated DPLL for synchronous clock transfer over air
- Built-in BERT tester for link quality evaluation
History and Developments
The development of the modem core began in 2010 at Modest Communications, which initially targeted the 20 GHz microwave region. It was developed for Altera Cyclone series FPGAs and supported bandwidth reached 120 MHz for a single channel in FDD mode. When Modesat was acquired by Xilinx, target technology shifted to Xilinx 7-series and the core was enhanced to 500 MHz and support for TDD mode was added.
Artec Design acquired the rights for the source code in 2017. Furthermore, most of the existing modem team continued the development of the modem at Artec Design. Afterwards, a second channel in XPI mode and sequential DSP at a higher clock rate allowed to use smaller Artix-7 devices for 1 GHz mode. Additionally, LDPC soft-decision FEC was designed to replace Reed-Solomon in more demanding applications.
Several clients from Europe, Asia and the US have evaluated or used the modem core, with the first products becoming production ready soon. Furthermore, development has been started to include the modem core in Vivado IP repository, which should be completed at the end of Q3 2019.