Modem IP is developed for a Xilinx Inc. FPGA’s.
Modem consists of baseband/data muxing and DSP cores. Development follows two directions: slower speed/cost effective and high bandwidth/more complex hardware.
Modem cores can be combined with frequency and spatial (xpic) combining. Data is split before transmission and combined after receive. Baseband combiner shifts modem core baseband to correct location in carrier and separates these in receiver. All cores have the following features:
• Fully digital carrier frequency error compensation
• Fully digital symbol clock recovery
• Compensation of Tx and Rx quadrature impairments in demodulator
• Rx and Tx group delay equalization
• I&Q frequency dependent imbalance compensation
• Recovery of low frequency components in demodulator
• integrated DPLL for synchronous clock transfer over air
• FDD and TDD (burst) modes with HW triggering interface for TDD
• Built-in diagnostics multiplexer for capturing data at several stages
• Debug utility and c library for core control
• Built-in BERT tester for link quality evaluation